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1. general description the p89v52x2 is an 80c51 microcontroller with 8 kb ?ash, 256 b of data ram, and 192 b of data eeprom. this device is designed to be a drop in and software compatible replacement for the p87c52, p87c52x2, p89c52, and p89c52x2 devices. 2. features 2.1 principal features n 0 mhz to 40 mhz operating frequency in 12 mode, 20 mhz in 6 mode n 8 kb of on-chip ?ash user code memory n 256 b of ram n enhanced uart n three 16-bit timers/counters n four 8-bit i/o ports n supports 12-clock (default) or 6-clock mode selection via software or in-circuit programming (icp) n dip40, plcc44, and lqfp44 packages n six interrupt sources with four priority levels n second dptr register 2.2 additional features n very low power n low emi mode (ale inhibit) n power-down mode with external interrupt wake-up n idle mode n extended temperature range n three security bits n programmable clock-out pin p89v52x2 8-bit 80c51 low power 8 kb ?ash microcontroller with 256 b ram, 192 b data eeprom rev. 03 4 may 2009 product data sheet
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 2 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 3. ordering information 4. block diagram table 1. ordering information type number package version name description p89v52x2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 p89v52x2fbd lqfp44 plastic low pro?le quad ?at package; 44 leads; body 10 10 1.4 mm sot389-1 p89v52x2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 fig 1. block diagram high performance 80c51 cpu 8 kb code flash 256 b data ram oscillator internal bus crystal or resonator 002aac565 uart port 2 port 0 port 1 timer 2 timer 0 timer 1 xtal1 xtal2 port 3 p3[7:0] p2[7:0] p1[7:0] p0[7:0] txd rxd t0 t1 t2 t2ex p89v52x2
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 3 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 5. pinning information 5.1 pinning fig 2. dip40 pin con?guration p89v52x2 p1[0]/t2 v dd p1[1]/t2ex p0[0]/ad0 p1[2] p0[1]/ad1 p1[3] p0[2]/ad2 p1[4] p0[3]/ad3 p1[5] p0[4]/ad4 p1[6] p0[5]/ad5 p1[7] p0[6]/ad6 rst p0[7]/ad7 p3[0]/rxd ea p3[1]/txd ale p3[2]/int0 psen p3[3]/int1 p2[7]/a15 p3[4]/t0 p2[6]/a14 p3[5]/t1 p2[5]/a13 p3[6]/wr p2[4]/a12 p3[7]/rd p2[3]/a11 xtal2 p2[2]/a10 xtal1 p2[1]/a9 v ss p2[0]/a8 002aac564 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 24 23 26 25 40 39 38 37 36 35 34 33 32 31 30 29 28 27
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 4 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 3. plcc44 pin con?guration fig 4. lqfp44 pin con?guration p89v52x2 p1[5] p0[4]/ad4 p1[6] p0[5]/ad5 p1[7] p0[6]/ad6 rst p0[7]/ad7 p3[0]/rxd n.c. p3[1]/txd p2[7]/a15 p3[4]/t0 p2[6]/a14 p3[5]/t1 p2[5]/a13 p1[4] p1[3] xtal2 p1[2] xtal1 p1[1]/t2ex v ss p1[0]/t2 n.c. n.c. p2[0]/a8 v dd p2[1]/a9 p0[0]/ad0 p2[2]/a10 p0[1]/ad1 p2[3]/a11 p0[2]/ad2 p2[4]/a12 p0[3]/ad3 002aac563 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 ea ale psen p3[6]/wr p3[7]/rd p3[3]/int1 p3[2]/int0 n.c. p89v52x2 002aac562 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 p1[5] p0[4]/ad4 p1[6] p0[5]/ad5 p1[7] p0[6]/ad6 rst p0[7]/ad7 p3[0]/rxd n.c. p3[1]/txd p2[7]/a15 p3[4]/t0 p2[6]/a14 p3[5]/t1 p2[5]/a13 p1[4] p1[3] xtal2 p1[2] xtal1 p1[1]/t2ex v ss p1[0]/t2 n.c. n.c. p2[0]/a8 v dd p2[1]/a9 p0[0]/ad0 p2[2]/a10 p0[1]/ad1 p2[3]/a11 p0[2]/ad2 p2[4]/a12 p0[3]/ad3 ea ale psen p3[6]/wr p3[7]/rd p3[3]/int1 p3[2]/int0 n.c.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 5 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 5.2 pin description table 2. pin description symbol pin type description dip40 lqfp44 plcc44 p0[0] to p0[7] i/o port 0: port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them ?oat, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external code and data memory. in this application, it uses strong internal pull-ups when transitioning to 1s. external pull-ups are required as a general purpose i/o port. p0[0]/ad0 39 37 43 i/o p0[0] port 0 bit 0. i/o ad0 address/data bit 0. p0[1]/ad1 38 36 42 i/o p0[1] port 0 bit 1. i/o ad1 address/data bit 1. p0[2]/ad2 37 35 41 i/o p0[2] port 0 bit 2. i/o ad2 address/data bit 2. p0[3]/ad3 36 34 40 i/o p0[3] port 0 bit 3. i/o ad3 address/data bit 3. p0[4]/ad4 35 33 39 i/o p0[4] port 0 bit 4. i/o ad4 address/data bit 4. p0[5]/ad5 34 32 38 i/o p0[5] port 0 bit 5. i/o ad5 address/data bit 5. p0[6]/ad6 33 31 37 i/o p0[6] port 0 bit 6. i/o ad6 address/data bit 6. p0[7]/ad7 32 30 36 i/o p0[7] port 0 bit 7. i/o ad7 address/data bit 7. p1[0] to p1[7] i/o with internal pull-up port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. the port 1 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 1 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. p1[5], p1[6], p1[7] have high current drive of 16 ma. p1[0]/t2 1 40 2 i/o p1[0] port 1 bit 0. i t2 external count input to timer/counter 2 or clock-out from timer/counter 2 p1[1]/t2ex 2 41 3 i/o p1[1] port 1 bit 1. i t2ex : timer/counter 2 capture/reload trigger and direction control p1[2] 3 42 4 i/o p1[2] port 1 bit 2. p1[3] 4 43 5 i/o p1[3] port 1 bit 3. p1[4] 5 44 6 i/o p1[4] port 1 bit 4. p1[5] 6 1 7 i/o p1[5] port 1 bit 5. p1[6] 7 2 8 i/o p1[6] port 1 bit 6.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 6 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom p1[7] 8 3 9 i/o p1[7] port 1 bit 7. p2[0] to p2[7] i/o with internal pull-up port 2 : port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 2 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. port 2 sends the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit address (movx@dptr). in this application, it uses strong internal pull-ups when transitioning to 1s. p2[0]/a8 21 18 24 i/o p2[0] port 2 bit 0. o a8 address bit 8. p2[1]/a9 22 19 25 i/o p2[1] port 2 bit 1. o a9 address bit 9. p2[2]/a10 23 20 26 i/o p2[2] port 2 bit 2. o a10 address bit 10. p2[3]/a11 24 21 27 i/o p2[3] port 2 bit 3. o a11 address bit 11. p2[4]/a12 25 22 28 i/o p2[4] port 2 bit 4. o a12 address bit 12. p2[5]/a13 26 23 29 i/o p2[5] port 2 bit 5. o a13 address bit 13. p2[6]/a14 27 24 30 i/o p2[6] port 2 bit 6. o a14 address bit 14. p2[7]/a15 28 25 31 i/o p2[7] port 2 bit 7. o a15 address bit 15. p3[0] to p3[7] i/o with internal pull-up port 3 : port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins are pulled high by the internal pull-ups when 1s are written to them and can be used as inputs in this state. as inputs, port 3 pins that are externally pulled low will source current (i il ) because of the internal pull-ups. p3[0]/rxd 10 5 11 i p3[0] port 3 bit 0. i rxd serial input port. p3[1]/txd 11 7 13 o p3[1] port 3 bit 1. o txd serial output port. p3[2]/ int0 12 8 14 i p3[2] port 3 bit 2. i int0 external interrupt 0 input. p3[3]/ int1 13 9 15 i p3[3] port 3 bit 3. i int1 external interrupt 1 input p3[4]/t0 14 10 16 i/o p3[4] port 3 bit 4. i t0 external count input to timer/counter 0. table 2. pin description continued symbol pin type description dip40 lqfp44 plcc44
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 7 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom [1] ale loading issue: when ale pin experiences higher loading (> 30 pf) during the reset, the microcontroller may accidentally enter into modes other than normal working mode. the solution is to add a pull-up resistor of 3 k w to 50 k w to v dd , e.g., for ale pin. [2] for 6-clock mode, ale is emitted at 1 3 of crystal frequency. p3[5]/t1 15 11 17 i/o p3[5] port 3 bit 5. i t1 external count input to timer/counter 1 p3[6]/ wr 16 12 18 o p3[6] port 3 bit 6. o wr external data memory write strobe p3[7]/ rd 17 13 19 o p3[7] port 3 bit 7. o rd external data memory read strobe. psen 29 26 32 i/o program store enable : psen is the read strobe for external program memory. when the device is executing from internal program memory, psen is inactive (high). when the device is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. rst 9 4 10 i reset : while the oscillator is running, a high logic state on this pin for two machine cycles will reset the device. ea 31 29 35 i external access enable : ea must be connected to v ss in order to enable the device to fetch code from the external program memory. ea must be strapped to v dd for internal program execution. ale 30 27 33 i/o address latch enable: ale is the output signal for latching the low byte of the address during an access to external memory. normally the ale [1] is emitted at a constant rate of 1 6 the crystal frequency [2] and can be used for external timing and clocking. one ale pulse is skipped during each access to external data memory. however, if ao is set to 1, ale is disabled. xtal1 19 15 21 i crystal 1 : input to the inverting oscillator ampli?er and input to the internal clock generator circuits. xtal2 18 14 20 o crystal 2: output from the inverting oscillator ampli?er. v dd 40 38 44 i power supply v ss 20 16 22 i ground table 2. pin description continued symbol pin type description dip40 lqfp44 plcc44
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 8 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6. functional description 6.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 9 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom table 3. special function registers [1] * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses msb lsb bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h -------- auxr auxiliary function register 8eh -------ao auxr1 auxiliary function register 1 a2h - - - gf2 0 - dps bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h -------- ckcon b register 8fh -------x2 dptr data pointer (2 b) dph data pointer high 83h -------- dpl data pointer low 82h -------- fmcon flash control register (r) f4h busy we - dap - - sv err flash control register (w) fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 fmdata flash data register f5h -------- fmadrh flash memory address high f6h -------- fmadrl flash memory address low f7h -------- bit address af ae ad ac ab aa a9 a8 ie* interrupt enable 0 a8h ea - et2 es et1 ex1 et0 ex0 bit address bf be bd bc bb ba b9 b8 ip* interrupt priority 0 b8h - - pt2 ps pt1 px1 pt0 px0 iph interrupt priority 0 high b7h - - pt2h ps0h pt1h px1h pt0h px0h bit address 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 bit address 97 96 95 94 93 92 91 90 p1*port 1 90h------ t2ex t2 bit address a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd pcon power control register 87h smod1 smod0 - pof gf1 gf0 pd idl
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 10 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom [1] unimplemented bits in sfrs (labeled -) are xs (unknown) at all times. unless otherwise speci?ed, 1s should not be writt en to these bits since they may be used for other purposes in future derivatives. the reset values shown for these bits are 0s although they are unknown when read. bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov - p rcap2h timer2 capture high cbh -------- rcap2l timer2 capture low cah -------- bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri sbuf serial port data buffer register 99h -------- saddr serial port address register a9h -------- saden serial port address enable b9h -------- sp stack pointer 81h -------- bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control register 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit address cf ce cd cc cb ca c9 c8 t2con* timer2 control register c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 t2mod timer2 mode control c9h ------ t2oe dcen th0 timer 0 high 8ch -------- th1 timer 1 high 8dh -------- th2 timer 2 high cdh -------- tl0 timer 0 low 8ah -------- tl1 timer 1 low 8bh -------- tl2 timer 2 low cch -------- tmod timer 0 and 1 mode 89h t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0 table 3. special function registers [1] continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses msb lsb
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 11 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.2 memory organization the various p89v52x2 memory spaces are as follows: ? data 128 b of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? i data indirect data. 256 b of internal data memory space (00h:ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 b immediately above it. ? sfr special function registers. selected cpu registers and peripheral control and status registers, accessible only via direct addressing. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89v52x2 has 8 kb of on-chip code memory. 6.3 system clock and clock options 6.3.1 clock input options and recommended capacitor values for the oscillator shown in figure 5 and figure 6 are the input and output of an internal inverting ampli?er (xtal1, xtal2), which can be con?gured for use as an on-chip oscillator. when driving the device from an external clock source, xtal2 should be left disconnected and xtal1 should be driven. power consumption can be further reduced by programming the extclk bit (ucfg.0). at start-up, the external oscillator may encounter a higher capacitive load at xtal1 due to interaction between the ampli?er and its feedback capacitance. however, the capacitance will not exceed 15 pf once the external signal meets the v il and v ih speci?cations. resonator manufacturer, supply voltage, and other factors may cause circuit performance to differ from one application to another. c 1 and c 2 should be adjusted appropriately for each design. t ab le 4 shows the typical values for c 1 and c 2 vs. resonator type for various frequencies. table 4. recommended values for c 1 and c 2 by crystal type resonator c 1 =c 2 quartz 20 pf to 30 pf ceramic 40 pf to 50 pf
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 12 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.3.2 clock control register (ckcon) by default, the device runs at twelve clocks per machine cycle. the device may be run in 6 clock per machine cycle mode by programming of either a non-volatile bit (fx2) or an sfr bit ( t ab le 5 cloc k modes ). if the fx2 non-volatile bit is programmed the device will run in 6-clock mode and the x2 sfr bit has no effect. if the fx2 bit is erased, then the clock mode is controlled by the x2 sfr bit. 6.4 ale control fig 5. oscillator characteristics (using the on-chip oscillator) fig 6. oscillator characteristics (external clock drive) 002aaa545 xtal2 xtal1 v ss c 1 c 2 002aaa546 xtal2 n.c. xtal1 external oscillator signal v ss table 5. clock modes fx2 clock mode bit (ucfg.1) x2 bit (clkcon.0) cpu clock mode erased 0 12-clock mode (default) erased 1 6-clock mode programmed x 6-clock mode table 6. auxr - auxiliary register (address 8eh) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol ------ -ao
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 13 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.5 dual data pointers the device has two 16-bit data pointers. the dptr select (dps) bit in auxr1 determines which of the two data pointers is accessed. when dps = 0, dptr0 is selected; when dps = 1, dptr1 is selected. quickly switching between the two data pointers can be accomplished by a single inc instruction on auxr1 (see figure 8 ). table 7. auxr - auxiliary register (address 8eh) bit description bit symbol description 7 to 1 - reserved for future use. should be set to 0 by user programs. 0 ao ale off: disables/enables ale. ao = 0 results in ale emitted at a constant rate of 1 2 the oscillator frequency. in case of ao = 1, ale is active only during a movx or movc. fig 7. internal and external data memory structure 00h ffh upper 128 b internal ram lower 128 b internal ram (indirect and direct addressing) (indirect addressing) (direct addressing) special function registers (sfrs) 80h ffh ffffh external data memory 0000h (indirect addressing) 80h 7fh 002aac567 fig 8. dual data pointer organization table 8. auxr1 - auxiliary register 1 (address a2h) bit allocation not bit addressable; reset value 00h bit 7 6 5 4 3 2 1 0 symbol ----gf20-dps dpl 82h dps = 0 ? dptr0 dps = 1 ? dptr1 external data memory dps 002aaa518 dph 83h dptr0 dptr1 auxr1 / bit0
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 14 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.6 reset at initial power-up, the port pins will be in a random state until the oscillator has started and the internal reset algorithm has weakly pulled all pins high. powering up the device without a valid reset could cause the device to start executing instructions from an indeterminate location. such unde?ned states may inadvertently corrupt the code in the ?ash. a system reset will not affect the on-chip ram while the device is running, however, the contents of the on-chip ram during power-up are indeterminate. when power is applied to the device, the rst pin must be held high long enough for the oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition to two machine cycles for a valid power-on reset. an example of a method to extend the rst signal is to implement a rc circuit by connecting the rst pin to v dd through a 10 m f capacitor and to v ss through an 8.2 k w resistor as shown in figure 9 . during initial power the pof ?ag in the pcon register is set to indicate an initial power-up condition. the pof ?ag will remain active until cleared by software. following a reset condition, under normal conditions, the device will start executing code from address 0000h in the users code memory. however if the requirements are met for icp entry, the device will enter icp mode. table 9. auxr1 - auxiliary register 1 (address a2h) bit description bit symbol description 7 to 4 - reserved for future use. should be set to 0 by user programs. 3 gf2 general purpose user-de?ned ?ag. 2 0 this bit contains a hard-wired 0. allows toggling of the dps bit by incrementing auxr1, without interfering with other bits in the register. 1 - reserved for future use. should be set to 0 by user programs. 0 dps data pointer select. chooses one of two data pointers for use by the program. see text for details. fig 9. power-on reset circuit 002aaa543 v dd v dd 8.2 k w rst xtal2 xtal1 c 1 c 2 10 m f
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 15 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.7 flash memory 6.7.1 flash organization the p89v52x2 program memory consists of an 8 kb block of user code. the ?ash can be read or written in bytes but may only be erased as an entire block. a chip erase function will erase the entire user code memory and its associated security bits. this ?ash memory can be erased or programmed using a programmer tool that supports icp. 6.7.2 features ? flash internal program memory. ? programming and erase over the full operating voltage range. ? programming with industry-standard commercial programmers. ? 10000 typical erase/program cycles for each byte. ? 100 year minimum data retention. 6.8 timers/counters 0 and 1 the two 16-bit timer/counter registers: timer 0 and timer 1 can be con?gured to operate either as timers or event counters (see t ab le 10 and t ab le 11 ). in the timer function, the register is incremented every machine cycle. thus, one can think of it as counting machine cycles. since a machine cycle consists of six oscillator periods, the count rate is 1 6 of the oscillator frequency. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register in the machine cycle following the one in which the transition was detected. since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1 12 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. in addition to the timer or counter selection, timer 0 and timer 1 have four operating modes from which to select. the timer or counter function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. table 10. tmod - timer/counter mode control register (address 89h) bit allocation not bit addressable; reset value: 0000 0000b; reset source(s): any source bit 7 6 5 4 3 2 1 0 symbol t1gate t1c/ t t1m1 t1m0 t0gate t0c/ t t0m1 t0m0
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 16 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom table 11. tmod - timer/counter mode control register (address 89h) bit description bit symbol description 7 t1gate gating control for timer 1. when set, timer/counter is enabled only while the int1 pin is high and the tr1 control pin is set. when cleared, timer 1 is enabled when the tr1 control bit is set. 6 t1c/ t timer or counter select for timer 1. cleared for timer operation (input from cclk). set for counter operation (input from t1 input pin). 5 t1m1 mode select for timer 1. 4 t1m0 3 t0gate gating control for timer 0. when set, timer/counter is enabled only while the int0 pin is high and the tr0 control pin is set. when cleared, timer 0 is enabled when the tr0 control bit is set. 2 t0c/ t timer or counter select for timer 0. cleared for timer operation (input from cclk). set for counter operation (input from t0 input pin). 1 t0m1 mode select for timer 0. 0 t0m0 table 12. tmod - timer/counter mode control register (address 89h) m1/m0 operating mode m1 m0 operating mode 0 0 0 8048 timer tlx serves as 5-bit prescaler 0 1 1 16-bit timer/counter thx and tlx' are cascaded; there is no prescaler. 1 0 2 8-bit auto-reload timer/counter thx holds a value which is to be reloaded into tlx each time it over?ows. 1 1 3 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 3 (timer 1) timer/counter 1 stopped. table 13. tcon - timer/counter control register (address 88h) bit allocation bit addressable; reset value: 0000 0000b; reset source(s): any reset bit 7 6 5 4 3 2 1 0 symbol tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 14. tcon - timer/counter control register (address 88h) bit description bit symbol description 7 tf1 timer 1 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the processor vectors to timer 1 interrupt routine, or by software. 6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter 1 on/off. 5 tf0 timer 0 over?ow ?ag. set by hardware on timer/counter over?ow. cleared by hardware when the processor vectors to timer 0 interrupt routine, or by software. 4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter 0 on/off.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 17 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.8.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a ?xed divide-by-32 prescaler. figure 10 shows mode 0 operation. in this mode, the timer register is con?gured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt ?ag tfn. the count input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn, to facilitate pulse width measurements). trn is a control bit in the special function register tcon ( figure 8 ). the gate bit is in the tmod register. the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run ?ag (trn) does not clear the registers. mode 0 operation is the same for timer 0 and timer 1 (see figure 10 ). there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). 6.8.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register (thn and tln) are used. see figure 11 . 3 ie1 interrupt 1 edge ?ag. set by hardware when external interrupt 1 edge/low-level is detected. cleared by hardware when the interrupt is processed, or by software. 2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low-level that triggers external interrupt 1. 1 ie0 interrupt 0 edge ?ag. set by hardware when external interrupt 0 edge/low-level is detected. cleared by hardware when the interrupt is processed, or by software. 0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low-level that triggers external interrupt 0. table 14. tcon - timer/counter control register (address 88h) bit description continued bit symbol description fig 10. timer/counter 0 or 1 in mode 0 (13-bit counter) 002aaa519 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (5-bits) thn (8-bits) tfn control overflow interrupt
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 18 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.8.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 12 . over?ow from tln not only sets tfn, but also reloads tln with the contents of thn, which must be preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 and timer 1. 6.8.4 mode 3 when timer 1 is in mode 3 it is stopped (holds its count). the effect is the same as setting tr1=0. timer 0 in mode 3 establishes tl0 and th0 as two separate 8-bit counters. the logic for mode 3 and timer 0 is shown in figure 13 . tl0 uses the timer 0 control bits: t0c/ t, t0gate, tr0, int0, and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications that require an extra 8-bit timer. with timer 0 in mode 3, the p89v52x2 can look like it has an additional timer. note: when timer 0 is in mode 3, timer 1 can be turned on and off by switching it into and out of its own mode 3. it can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt. fig 11. timer/counter 0 or 1 in mode 1 (16-bit counter) 002aaa520 osc/6 tn pin trn tngate intn pin c/t = 0 c/t = 1 tln (8-bits) thn (8-bits) tfn control overflow interrupt fig 12. timer/counter 0 or 1 in mode 2 (8-bit auto-reload) 002aaa521 osc/6 tn pin trn tngate intn pin tln (8-bits) thn (8-bits) tfn control overflow reload interrupt c/t = 0 c/t = 1
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 19 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.9 timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t2 in the special function register t2con. timer 2 has four operating modes: capture, auto-reload (up or down counting), clock-out, and baud rate generator which are selected according to t ab le 15 using t2con ( t ab le 16 and t ab le 17 ) and t2mod ( t ab le 18 and t ab le 19 ). fig 13. timer/counter 0 mode 3 (two 8-bit counters) 002aaa522 osc/2 tr1 tr0 tngate int0 pin tl0 (8-bits) tf0 control overflow interrupt th0 (8-bits) tf1 control overflow interrupt osc/6 t0 pin c/t = 0 c/t = 1 table 15. timer 2 operating mode rclk+tclk cp/ rl2 tr2 t2oe mode 0010 16-bit auto reload 0110 16-bit capture 0011 programmable clock-out 1 x 1 0 baud rate generator xx0 xoff table 16. t2con - timer/counter 2 control register (address c8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 table 17. t2con - timer/counter 2 control register (address c8h) bit description bit symbol description 7 tf2 timer 2 over?ow ?ag set by a timer 2 over?ow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1 or when timer 2 is in clock-out mode. 6 exf2 timer 2 external ?ag is set when timer 2 is in capture, reload or baud rate mode, exen2 = 1 and a negative transition on t2ex occurs. if timer 2 interrupt is enabled exf2 = 1 causes the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. 5 rclk receive clock ?ag. when set, causes the uart to use timer 2 over?ow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 over?ow to be used for the receive clock.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 20 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.9.1 capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2 = 0 timer 2 is a 16-bit timer or counter (as selected by c/ t2 in t2con) which upon over?owing sets bit tf2, the timer 2 over?ow bit. the capture mode is illustrated in figure 14 . 4 tclk transmit clock ?ag. when set, causes the uart to use timer 2 over?ow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 over?ows to be used for the transmit clock. 3 exen2 timer 2 external enable ?ag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. 2 tr2 start/stop control for timer 2. a logic 1 enables the timer to run. 1c/ t2 timer or counter select. (timer 2) 0 = internal timer (f osc /6) 1 = external event counter (falling edge triggered; external clocks maximum rate = f osc /12 0 cp/ rl2 capture/reload ?ag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 over?ows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 over?ow. table 18. t2mod - timer 2 mode control register (address c9h) bit allocation not bit addressable; reset value: xx00 0000b bit 7 6 5 4 3 2 1 0 symbol - - - - - - t2oe dcen table 19. t2mod - timer 2 mode control register (address c9h) bit description bit symbol description 7 to 2 - reserved for future use. should be set to 0 by user programs. 1 t2oe timer 2 output enable bit. used in programmable clock-out mode only. 0 dcen down count enable bit. when set, this allows timer 2 to be con?gured as an up/down-counter. table 17. t2con - timer/counter 2 control register (address c8h) bit description continued bit symbol description
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 21 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ien0 register). if exen2 = 1, timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 like tf2 can generate an interrupt (which vectors to the same location as timer 2 over?ow interrupt). the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt. there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2 pin transitions or f osc /6 pulses. since once loaded contents of rcap2l and rcap2h registers are not protected, once timer2 interrupt is signalled it has to be serviced before new capture event on t2ex pin occurs. otherwise, the next falling edge on t2ex pin will initiate reload of the current value from tl2 and th2 to rcap2l and rcap2h and consequently corrupt their content related to previously reported interrupt. 6.9.2 auto-reload mode (up or down-counter) in the 16-bit auto-reload mode, timer 2 can be con?gured as either a timer or counter (via c/ t2 in t2con), then programmed to count up or down. the counting direction is determined by bit dcen (down-counter enable) which is located in the t2mod register (see t ab le 18 and t ab le 19 ). when reset is applied, dcen = 0 and timer 2 will default to counting up. if the dcen bit is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 15 shows timer 2 counting up automatically (dcen = 0). fig 14. timer 2 in capture mode 002aaa523 osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control capture tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 22 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom in this mode, there are two options selected by bit exen2 in t2con register. if exen2 = 0, then timer 2 counts up to 0ffffh and sets the tf2 (over?ow flag) bit upon over?ow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software means. auto reload frequency when timer 2 is counting up can be determined from this formula: (1) where supplyfrequency is either f osc (c/ t2 = 0) or frequency of signal on t2 pin (c/ t2 = 1). if exen2 = 1, a 16-bit reload can be triggered either by an over?ow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 is 1. microcontrollers hardware will need three consecutive machine cycles in order to recognize falling edge on t2ex and set exf2 = 1: in the ?rst machine cycle pin t2ex has to be sampled as 1; in the second machine cycle it has to be sampled as 0, and in the third machine cycle exf2 will be set to 1. in figure 16 , dcen = 1 and timer 2 is enabled to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex timer 2 will count up. timer 2 will over?ow at 0ffffh and set the tf2 ?ag, which can then generate an interrupt, if the interrupt is enabled. this timer over?ow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. fig 15. timer 2 in auto-reload mode (dcen = 0) 002aaa524 osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) tf2 control reload tr2 timer 2 interrupt exf2 rcap2l rcap2h control exen2 transition detector t2ex pin supplyfrequency 65536 rcap2h rcap2l , () e () ------------------------------------------------------------------------------- -
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 23 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom when a logic 0 is applied at pin t2ex this causes timer 2 to count down. the timer will under?ow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. timer 2 under?ow sets the tf2 ?ag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external ?ag exf2 toggles when timer 2 under?ows or over?ows. this exf2 bit can be used as a 17th bit of resolution if needed. 6.9.3 programmable clock-out a 50 % duty cycle clock can be programmed to come out on pin t2 (p1[0]). this pin, besides being a regular i/o pin, has two additional functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50 % duty cycle clock ranging from 122 hz to 8 mhz at a 16 mhz operating frequency. to con?gure the timer/counter 2 as a clock generator, bit c/ t2 (in t2con) must be cleared and bit t2oe in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in equation 2 : (2) where (rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 rollovers will not generate an interrupt. this is similar to when it is used as a baud rate generator. 6.9.4 baud rate generator mode bits tclk and/or rclk in t2con allow the uart transmit and receive baud rates to be derived from either timer 1 or timer 2 (see section 6.10 for details). when tclk = 0, timer 1 is used as the uart transmit baud rate generator. when tclk = 1, timer 2 is fig 16. timer 2 in auto reload mode (dcen = 1) 002aaa525 tl2 (8-bits) th2 (8-bits) tf2 exf2 underflow timer 2 interrupt rcap2l rcap2h ffh ffh overflow (down-counting reload value) (up-counting reload value) count direction 1 = up 0 = down t2ex pin toggle osc ? 6 t2 pin c/t2 = 0 c/t2 = 1 control tr2 oscillatorfrequency 2 65536 rcap2h rcap2l , () e () -----------------------------------------------------------------------------------------
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 24 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom used as the uart transmit baud rate generator. rclk has the same effect for the uart receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates C timer 1 or timer 2. figure 17 shows timer 2 in baud rate generator mode: the baud rate generation mode is like the auto-reload mode, when a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2s over?ow rate given below: modes 1 and 3 baud rates = timer 2 over?ow rate/16 the timer can be con?gured for either timer or counter operation. in many applications, it is con?gured for timer' operation (c/ t2 = 0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1 6 the oscillator frequency). as a baud rate generator, it increments at the oscillator frequency. thus the baud rate formula is as follows: modes 1 and 3 baud rates = (3) where: (rcap2h, rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable ?ag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external ?ag) but will not cause a reload from (rcap2h, rcap2l) to (th2, tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. fig 17. timer 2 in baud rate generator mode 002aaa526 tx/rx baud rate timer 2 interrupt osc ? 2 t2 pin c/t2 = 0 c/t2 = 1 tl2 (8-bits) th2 (8-bits) control tr2 exf2 rcap2l rcap2h control exen2 transition detector t2ex pin reload oscillatorfrequency 16 65536 rcap2h rcap2l , () C () () ----------------------------------------------------------------------------------------------- -
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 25 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. t ab le 20 shows commonly used baud rates and how they can be obtained from timer 2. 6.9.5 summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2 (p1[0]) the baud rate is: baud rate = timer 2 over?ow rate/16 if timer 2 is being clocked internally, the baud rate is: baud rate = f osc /(16 (65536 - (rcap2h, rcap2l))) where f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l = 65536 - f osc /(16 baud rate) 6.10 uart the uart operates in all standard modes. enhancements over the standard 80c51 uart include framing error detection, and automatic address recognition. 6.10.1 mode 0 serial data enters and exits through rxd and txd outputs the shift clock. only 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 6 of the cpu clock frequency. uart con?gured to operate in this mode outputs serial clock on txd line no matter whether it sends or receives data on rxd line. table 20. timer 2 generated commonly used baud rates rate oscillator frequency timer 2 rcap2h rcap2l 750 kbd 12 mhz ff ff 19.2 kbd 12 mhz ff d9 9.6 kbd 12 mhz ff b2 4.8 kbd 12 mhz ff 64 2.4 kbd 12 mhz fe c8 600 bd 12 mhz fb 1e 220 bd 12 mhz f2 af 600 bd 6 mhz fd 8f 220 bd 6 mhz f9 57
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 26 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.10.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 2 over?ow rate. 6.10.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logical 1). when data is transmitted, the 9th data bit (tb8 in scon) can be assigned the value of 0 or (e.g. the parity bit (p, in the psw) could be moved into tb8). when data is received, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 6.10.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9th data bit, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 2 over?ow rate. table 21. scon - serial port control register (address 98h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol sm0/fe sm1 sm2 ren tb8 rb8 ti ri table 22. scon - serial port control register (address 98h) bit description bit symbol description 7 sm0/fe the usage of this bit is determined by smod0 in the pcon register. if smod0 = 0, this bit is sm0, which with sm1, de?nes the serial port mode. if smod0 = 1, this bit is fe (framing error). fe is set by the receiver when an invalid stop bit is detected. once set, this bit cannot be cleared by valid frames but can only be cleared by software. (note: it is recommended to set up uart mode bits sm0 and sm1 before setting smod0 to 1.) 6 sm1 with sm0, de?nes the serial port mode (see t ab le 23 below). 5 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. 4 ren enables serial reception. set by software to enable reception. clear by software to disable reception. 3 tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 27 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.10.5 framing error framing error (fe) is reported in the scon.7 bit if smod0 (pcon.6) = 1. if smod0 = 0, scon.7 is the sm0 bit for the uart, it is recommended that sm0 is set up before smod0 is set to 1. 6.10.6 more about uart mode 1 reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the ?rst bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. 6.10.7 more about uart modes 2 and 3 reception is performed in the same manner as in mode 1. 2 rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is unde?ned. 1 ti transmit interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or at the stop bit in the other modes, in any serial transmission. must be cleared by software. 0 ri receive interrupt ?ag. set by hardware at the end of the 8th bit time in mode 0, or approximately halfway through the stop bit time in all other modes. (see sm2 for exceptions). must be cleared by software. table 23. scon - serial port control register (address 98h) sm0/sm1 mode de?nition sm0, sm1 uart mode baud rate 0 0 0: shift register cpu clock/6 0 1 1: 8-bit uart variable 1 0 2: 9-bit uart cpu clock/32 or cpu clock/16 1 1 3: 9-bit uart variable table 22. scon - serial port control register (address 98h) bit description continued bit symbol description
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 28 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the ?nal shift pulse is generated: (a) ri = 0, and (b) either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the ?rst 8 data bits go into sbuf. 6.10.8 multiprocessor communications uart modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received or transmitted. when data is received, the 9th bit is stored in rb8. the uart can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. one way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it ?rst sends out an address byte which identi?es the target slave. an address byte differs from a data byte in a way that the 9th bit is 1 in an address byte and 0 in the data byte. with sm2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is 0. however, an address byte having the 9th bit set to 1 will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. the addressed slave will clear its sm2 bit and prepare to receive the data (still 9 bits long) that follow. the slaves that werent being addressed leave their sm2 bits set and go on about their business, ignoring the subsequent data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit, although this is better done with the framing error ?ag. when uart receives data in mode 1 and sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. 6.10.9 automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled for the uart by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt ?ag (ri) will be automatically set when the received byte contains either the given address or the broadcast' address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to de?ne the slaves address, saddr, and the address mask, saden. saden is used to de?ne which bits in the saddr are to be used and which bits are dont care. the saden mask can be logically anded with the saddr to create the given address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. this device uses the methods presented in figure 18 to determine if a given or broadcast address has been received or not.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 29 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom the following examples will help to show the versatility of this scheme. example 1, slave 0: (4) example 2, slave 1: (5) in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bi t0=0(forslave0)andbit1=0(forslave1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: example 1, slave 0: fig 18. schemes used by the uart to detect given and broadcast addresses when multiprocessor communications is enabled 002aaa527 rx_byte(7) saddr(7) saden(7) rx_byte(0) saddr(0) . . . given_address_match logic used by uart to detect 'given address' in received data saddr(7) saden(7) rx_byte(7) saddr(0) saden(0) rx_byte(0) broadcast_address_match logic used by uart to detect 'given address' in received data saden(0) . . . saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1110 given = 1100 000x --------------------------------------------------- -
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 30 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom (6) example 2, slave 1: (7) example 2, slave 2: (8) in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bi t1=0 and it can be uniquely addressed by 1110 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as dont-cares. in most cases, interpreting the dont-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr and saden are loaded with 0s. this produces a given address of all dont cares as well as a broadcast address of all dont cares'. this effectively disables the automatic addressing mode and allows the microcontroller to use standard uart drivers which do not make use of this feature. 6.11 interrupt priority and polling sequence the device supports six interrupt sources under a four level priority scheme. t ab le 24 summarizes the polling sequence of the supported interrupts. (see figure 19 ). saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 --------------------------------------------------- - saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x --------------------------------------------------- - saddr = 1100 0000 saden = 1111 1100 given = 1100 00xx --------------------------------------------------- - table 24. interrupt polling sequence description interrupt ?ag vector address interrupt enable interrupt priority service priority wake-up power-down external interrupt 0 ie0 0003h ex0 px0/h 1 (highest) yes t0 tf0 000bh et0 pt0/h 2 no external interrupt 1 ie1 0013h ex1 px1/h 3 yes t1 tf1 001bh et1 pt1/h 4 no uart ti/ri 0023h es0 ps0/h 5 no t2 tf2, exf2 003bh et2 pt2/h 6 no
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 31 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 19. interrupt structure 002aac568 highest priority interrupt interrupt polling sequence int0# ie and iea registers ip/iph/ipa/ipah registers individual enables global disable ie0 0 1 it0 lowest priority interrupt tf0 int1# tf1 ri ti tf2 exf2 ie1 0 1 it1 table 25. ie - interrupt enable register (address a8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol ea - et2 es et1 ex1 et0 ex0 table 26. ie - interrupt enable register (address a8h) bit description bit symbol description 7 ea interrupt enable bit: ea = 1 interrupt(s) can be serviced, ea = 0 interrupt servicing disabled. 6 - reserved 5 et2 timer 2 over?ow interrupt enable 4 es serial port interrupt enable 3 et1 timer 1 over?ow interrupt enable.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 32 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.12 power-saving modes the device provides two power saving modes of operation for applications where power consumption is critical. the two modes are idle and power-down, see t ab le 31 . 6.12.1 idle mode idle mode is entered setting the idl bit in the pcon register. in idle mode, the program counter is stopped. the system clock continues to run and all interrupts and peripherals remain active. the on-chip ram and the special function registers hold their data during this mode. 2 ex1 external interrupt 1 enable. 1 et0 timer 0 over?ow interrupt enable. 0 ex0 external interrupt 0 enable. table 27. ip - interrupt priority low register (address b8h) bit allocation bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - pt2 ps pt1 px1 pt0 px0 table 28. ip - interrupt priority low register (address b8h) bit description bit symbol description 7:6 - reserved 5 pt2 timer 2 interrupt priority low bit. 4 ps serial port interrupt priority low bit. 3 pt1 timer 1 interrupt priority low bit. 2 px1 external interrupt 1 priority low bit. 1 pt0 timer 0 interrupt priority low bit. 0 px0 external interrupt 0 priority low bit. table 29. iph - interrupt priority high register (address b7h) bit allocation not bit addressable; reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - pt2h psh pt1h px1h pt0h px0h table 30. iph - interrupt priority high register (address b7h) bit description bit symbol description 7:6 - reserved 5 pt2h timer 2 interrupt priority high bit. 4 psh serial port interrupt priority high bit. 3 pt1h timer 1 interrupt priority high bit. 2 px1h external interrupt 1 priority high bit. 1 pt0h timer 0 interrupt priority high bit. 0 px0h external interrupt 0 priority high bit. table 26. ie - interrupt enable register (address a8h) bit description continued bit symbol description
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 33 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom the device exits idle mode through either a system interrupt or a hardware reset. exiting idle mode via system interrupt, the start of the interrupt clears the idl bit and exits idle mode. after exit the interrupt service routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the idle mode. a hardware reset starts the device similar to a power-on reset. 6.12.2 power-down mode the power-down mode is entered by setting the pd bit in the pcon register. in the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only. sram contents are retained during power-down, the minimum v dd level is 2.0 v. the device exits power-down mode through either an enabled external level sensitive interrupt or a hardware reset. the start of the interrupt clears the pd bit and exits power-down. holding the external interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bringing back high to complete the exit. upon interrupt signal restored to logic v ih , the interrupt service routine program execution resumes beginning at the instruction immediately following the instruction which invoked power-down mode. a hardware reset starts the device similar to power-on reset. to exit properly out of power-down, the reset or external interrupt should not be executed before the v dd line is restored to its normal operating voltage. be sure to hold v dd voltage long enough at its normal operating level for the oscillator to restart and stabilize (normally less than 10 ms). 6.13 data eeprom the p89v52x2 contains 192 b of data eeprom organized into three pages of 64 b each. this memory can be erased in 64 byte pages (using a page erase command) or erased and written as bytes. the p89v52x2 ?ash reliably stores memory contents even after 100000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. p89v52x2 uses v dd as the supply voltage to perform the program/erase algorithms. table 31. power-saving modes mode initiated by state of device exited by idle mode software (set idl bit in pcon) mov pcon, #01h; clk is running. interrupts, serial port and timers/counters are active. program counter is stopped. ale and psen signals at a high-level during idle. all registers remain unchanged. enabled interrupt or hardware reset. start of interrupt clears idl bit and exits idle mode, after the interrupt service routine reti instruction, program resumes execution beginning at the instruction following the one that invoked idle mode. a hardware reset restarts the device similar to a power-on reset. power-down mode software (set pd bit in pcon) mov pcon, #02h; clk is stopped. on-chip sram and sfr data is maintained. ale and psen signals at a low-level during power-down. external interrupts are only active for level sensitive interrupts, if enabled. enabled external level sensitive interrupt or hardware reset. start of interrupt clears pd bit and exits power-down mode, after the interrupt service routine reti instruction program resumes execution beginning at the instruction following the one that invoked power-down mode. a hardware reset restarts the device similar to a power-on reset.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 34 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom the data eeprom must be mapped into the code memory address space in order to read, erase, or program the data eeprom. the memory is read using the movc instruction. 6.13.1 features ? icp with industry-standard commercial programmers ? iap-lite allows individual and multiple bytes of data eeprom to be programmed under control of the end application. ? programming and erase over the full operating voltage range ? programming/erase using icp or iap-lite ? program or erases requires 2 ms, 4 ms, or 6 ms, depending on the operation ? programmable security for the data in each page ? > 100000 typical erase/program cycles for each byte ? data eeprom mapped into code space for quick movc reading 6.13.2 register interface erasing, programming, and mapping operations are performed in the application under the control of the microcontrollers ?rmware using four sfrs and an internal 64-byte page register. these sfrs are: ? fmcon (flash control register). when read, this is the status register. when written, this is a command register. note that the status bits are cleared to logic 0s when the command is written. ? fmadrl, fmadrh (flash memory address low, flash memory address high). used to specify the byte address within the page register or specify the page within user code memory (for programming, erase, and reading the data eeprom is mapped into the user address space (see t ab le 32 ). ? fmdata (flash data register). accepts data to be loaded into the page register. data is read by mapping the data eeprom into the code memory space and using the movc instruction. 6.13.3 mapping the data eeprom into code space in order to read, erase, or program the data eeprom must be mapped into the code memory address space. this is accomplished by writing the map command (09h) to fmcon. the data eeprom may be unmapped by writing the unmap command (0ah) to fmcon. the mapping of the data eeprom pages into code memory space is shown in t ab le 32 . 6.13.4 reading the data eeprom reading the data eeprom can be achieved by performing the following sequence: table 32. data eeprom page addresses data eeprom page start address end address 0 ff00h ff3fh 1 ff40h ff7fh 2 ff80h ffbfh
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 35 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom ? map the data eeprom into code memory space if not already mapped. ? write the data eeprom byte address into the dptr. ? use the movc instruction to read the data eeprom. 6.13.5 erasing a complete page (64 b) a complete page can be erased by performing the following sequence: ? map the data eeprom into code memory space if not already mapped. ? write the lower 8-bits of the data eeprom pages start address into fmadrl. ? write the ers_dp command (33h) to fmcon. once the ers_dp command is written to fmcon, code execution will stall until the operation is completed, approximately 6 ms. 6.13.6 data eeprom programming and erasing using the page register in addition to page erase, a 64 b page register is included which allows from 1 b to 64 b of a given page to be programmed or erase/programmed at the same time, substantially reducing overall programming time. two programming operations are provided: ? program only operation. this operation used the prog (48h) command and programs the contents of the page register into the data eeprom page. this operation requires that the bytes being programmed have been previously erased. this operation requires approximately 2 ms to complete. ? erase and program operation. this operation uses the ep (68h) command to both erase and program the bytes previously loaded into the page register. this command is often useful to erase and reprogram a single byte of data. this operation requires approximately 4 ms to complete. the page register consists of 64 b and an update ?ag for each byte. when a load command is issued to fmcon the page register contents and all of the update ?ags will be cleared. when fmdata is written, the value written to fmdata will be stored in the page register at the location speci?ed by the lower 6 bits of fmadrl. in addition, the update ?ag for that location will be set. fmadrl will auto-increment to the next location. auto-increment after writing to the last byte in the page register will wrap-around to the ?rst byte in the page register, but will not affect fmadrl[7:6]. bytes loaded into the page register do not have to be continuous. any byte location can be loaded into the page register by changing the contents of fmadrl prior to writing to fmdata. however, each location in the page register can only be written once following each load command. attempts to write to a page register location more than once should be avoided. fmadrh and fmadrl[7:6] are used to specify a page in the code memory space. when the prog command is written to fmcon, the locations within the data eeprom page that correspond to updated locations in the page register will have their contents programmed with the contents of their corresponding locations in the page register. only the bytes that were loaded into the page register will be programmed in the data eeprom array. other bytes within the data eeprom array will not be affected. the ep command works similarly except that if the ep command is written, the corresponding bytes in the data eeprom will be erased prior to being programmed. this is often useful for erasing and programming a small number of bytes or even a single byte.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 36 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom writing either the prog or ep command to fmcon will start the program or erase-program process and place the cpu in a program-idle state. the cpu will remain in this idle state until the program or erase-program cycle is completed. interrupts will not be serviced until the cycle is completed. erase-program or programming of a single byte (or multiple bytes) in the data eeprom array is accomplished using the following steps: ? write the load command (00h) to fmcon. the load command will clear all locations in the page register and their corresponding update ?ags. ? write the address within the page register to fmadrl. since the loading the page register uses fmadrl[5:0], and since the erase-program or program command uses fmadrh and fmadrl[7:6], the user can write the byte location within the page register (fmadrl[5:0]) and the code memory page address (fmadrh and fmadrl[7:6]) at this time. ? write the data to be programmed to fmdata. this will increment fmadrl pointing to the next byte in the page register. ? write the address of the next byte to be programmed to fmadrl, if desired. (this is not needed for contiguous bytes since fmadrl is auto-incremented). all bytes to be programmed must be within the same page. ? write the data for the next byte to be programmed to fmdata. ? repeat writing of fmadrl and/or fmdata until all desired bytes have been loaded into the page register. ? write the page address mapped into user code memory to fmadrh and fmadrl[7:6], if not previously included when writing the page register address to fmadrl[5:0]. ? write the ep (68h) or prog (48h) command to fmcon, starting the erase-program or program cycle. ? read fmcon to check status. if aborted, repeat starting with the load command. table 33. flash memory control register (fmcon - address f4h) bit allocation bit 7 6 5 4 3 2 1 0 symbol (r) busy we - dap - - sv err symbol (w) fmcmd.7 fmcmd.6 fmcmd.5 fmcmd.4 fmcmd.3 fmcmd.2 fmcmd.1 fmcmd.0 reset 00000000
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 37 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom an assembly language routine to load the page register and perform an erase/program operation is shown below. this code assumes the data eeprom has been mapped into user code space. ;************************************************** ;* pgm user code * ;************************************************** ;* * ;* inputs: * ;*r3 = number of bytes to program (byte) * ;*r4 = page address msb(byte) * ;*r5 = page address lsb(byte) * ;*r7 = pointer to data buffer in ram(byte) * ;* outputs: * ;*r7 = status (byte) * ;* c = clear on no error, set on error * ;************************************************** table 34. flash memory control register (fmcon - address e4h) bit description bit symbol access description 0 err r set when either of the following conditions occur: ? device was reset before the operation was completed. ? attempt made to access data eeprom while data access protect (dap) is set. ? an error occurs in the devices internal high voltage circuits. fmcmd.0 w command byte bit 0. 1 sv r security violation. set when an attempt is made to program, erase, or crc a secured page. the speci?c cause of the security violation depends on the operation: ? prog or ep : csec.0 = 1 or dpxsec.1 = 1 for the page addressed by fmadrh/l. ? ers_g : any dpxsec.0 = 1. ? ers_dp : dpxsec.2 = 1 for addressed page while in execution mode. ? crc_dp : dpxcsec.0 = 1 and dpxsec.1 = 0. fmcmd.1 w command byte bit 1 2 - r reserved fmcmd.2 w command byte bit 2. 3 - r reserved fmcmd.3 w command byte bit 3. 4 dap r data access protect. when set, access to the data eeprom is unmapped and thus prohibited. set by the map command. cleared by the unmap command. fmcmd.4 w command byte bit 4. 5 - r reserved fmcmd.5 w command byte bit 5. 6 we r when set, indicates that data eeprom writes during program execution are enabled. fmcmd.6 w command byte bit 6. 7 busy r indicates that a program, erase, crc calculation or similar operation is in progress. note that this bit is usable only in icp mode since the cpu is stalled whenever this bit is set in execution mode. fmcmd.7 w command byte bit 7.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 38 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom load equ 00h ep equ 68h pgm_user: mov fmcon,#load ;load command, clears page register mov fmadrh,r4 ;get high address mov fmadrl,r5 ;get low address mov a,r7 ; mov r0,a ;get pointer into r0 load_page: mov fmdat,@r0 ;write data to page register inc r0 ;point to next byte djnz r3,load_page ;do until count is zero mov fmcon,#ep ;else erase & program the page mov r7,fmcon ;copy status for return mov a,r7 ;read status anl a,#0fh ;save only four lower bits jnz bad ; clr c ;clear error flag if good ret ;and return bad: setb c ;set error flag ret ;and return a c-language routine to load the page register and perform an erase/program operation is shown below. this code assumes the data eeprom has been mapped into user code space. #include unsigned char idata dbytes[64];// data buffer unsigned char fm_stat;// status result bit pgm_user (unsigned char, unsigned char); bit prog_fail; void main () { prog_fail=pgm_user(0x1f,0xc0); } bit pgm_user (unsigned char page_hi, unsigned char page_lo) { #define load0x00// clear page register, enable loading #define ep0x68// erase & program page unsigned char i;// loop count fmcon = load;//load command, clears page reg fmadrh = page_hi;// fmadrl = page_lo;//write my page address to addr regs for(i=0;i<64;i=i+1) {
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 39 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fmdata = dbytes[i]; } fmcon = ep;//erase & prog page command fm_stat = fmcon;//read the result status if ((fm_stat & 0x0f)!=0) prog_fail=1; else prog_fail=0; return(prog_fail); } 6.13.7 data eeprom write enable the data eeprom has a write enable mechanism to help prevent against inadvertent writes. if the we bit (fmcon.6) is set writes to the data eeprom are enabled. when cleared, writes are disabled. this bit only affects execution mode. the we bit is set when: ? the disable write enable bit, diswe (ucfg.2) = 1 ? in icp mode ? the set_we (08h) command is written to fmcon followed by the key value (96h) being written to fmdata the we bit is cleared following any reset. the we bit may also be cleared by writing the clr_we (0bh) command to fmcon. 6.13.8 data eeprom security bits the data eeprom security bits protects each data eeprom page. the data eeprom page security bits and their effects are shown in t ab le 35 . 6.13.9 summary of data eeprom commands t ab le 37 is a summary of the fmcon commands related to the data eeprom. table 35. dpxsec - data page x security register bit allocation bit 7 6 5 4 3 2 1 0 symbol - - - - - xersx pwrx movcx table 36. dpxsec - data page x security register bit description bit symbol description 7 to 3 - reserved 2 xersx execution erase protect x. when programmed = 1, cannot be erased with ers_dp command in execution mode. ers_dp can be used in icp mode. 1 pwrx page write protect x. when programmed = 1, data eeprom cannot be erased or programmed using prog or ep commands. 0 movcx when programmed = 1, prevents instructions fetched from off-chip from reading the contents of the data eeprom and returns ffh. crc_dp are disabled if the corresponding page write protect is disabled.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 40 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.14 user con?guration bytes this device contains some non-volatile bytes which allow the user to con?gure the device. these bytes are programmed or read using the con?guration read or write command (conf) with a programmer that supports icp. the user con?guration bytes, their conf address are shown in t ab le 38 . 6.15 ucfg the user con?guration bits in the ucfg register allow the user to con?gure some of the operating characteristics of the device and are shown in t ab le 39 . table 37. summary of data eeprom commands mnemonic value (hex) description clr_we 0b clear the we bit crc_dp 1d calculate crc on selected data eeprom page ep 68 erase and program data eeprom page ers_dp 33 erase data eeprom page load 00 reset and clear page register map 09 map data eeprom into upper end of user code space prog 48 program data eeprom page set_we 08 set the we bit if followed by writing key value to fmdata unmap 0a unmap data eeprom from user code space table 38. user con?guration bytes con?guration byte conf address function ucfg 00h 6x/12x selection, ext clk select, disable we csec 01h code security dp0sec 02h data eeprom, page 0, security dp1sec 03h data eeprom, page 1, security dp2sec 04h data eeprom, page 2, security mfg_id 10h manufacturer signature byte devic_id 11h device id signature byte deriv_id 12h derivative id signature byte table 39. ucfg - user con?guration register bit allocation bit 7 6 5 4 3 2 1 0 symbol - - - - - enw fx2 extclk
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 41 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 6.16 code security (csec) bits the code security bits protect against software piracy and prevent the contents of the ?ash from being read by unauthorized parties. the code security bits and their effects are shown in t ab le 41 . table 40. ucfg - user con?guration register bit description bit symbol description 7 to 3 - reserved 2 enw enable write. when programmed = 1, forces the we bit to be set. 1 fx2 force x2. when programmed = 1, the device is in 6-clock mode. when erased = 0, the mode depends on the state of the x2 bit in ckcon. 0 extclk external clock. when programmed = 1, disables the xtal block when using an external digital clock source. table 41. csec - code security register bit allocation bit 7 6 5 4 3 2 1 0 symbol - - - - - - intexec prot table 42. csec - code security register bit description bit symbol description 7 to 2 - reserved 1 intexec internal execution only. when programmed, if the internal address space is exceeded, the address will rollover into internal space (upper address bits are ignored) for movc and instruction fetches. movc will access the data eeprom when the address >= ff00h. 0 prot protect. when programmed, prohibits further erasing or programming of code memory. movc instructions executed from external code memory are disabled from fetching code bytes from internal code memory.
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 42 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 7. limiting values 8. static characteristics table 43. limiting values in accordance with the absolute maximum rating system (iec 60134). parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. symbol parameter conditions min max unit t amb(bias) bias ambient temperature - 55 +125 c t stg storage temperature - 65 +150 c v n voltage on any other pin except v ss , with respect to v dd - 0.5 v dd + 0.5 v i ol(i/o) low-level output current per input/output pin -15ma p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w table 44. static characteristics t amb = - 40 c to +85 c; v dd = 2.7 v to 5.5 v; v ss =0v symbol parameter conditions min typ max unit n endu(?) endurance of ?ash memory jedec standard a117 [1] 10000 - cycles t ret(?) ?ash memory retention time jedec standard a103 [1] 100 - years i latch i/o latch-up current jedec standard 78 [1] 100 + i dd -ma v il low-level input voltage - 0.5 - 0.3v dd v v ih high-level input voltage 0.7v dd - 6.0 v v ol low-level output voltage v dd = 4.5 v [2] [3] [4] - i ol = 3.2 ma - - 0.4 v v oh high-level output voltage v dd = 2.7 v, ports 1, 2, 3 [5] - i oh = - 20 m av dd - 0.7 - - v v dd = 4.5 v, ports 1, 2, 3 [5] - i oh = - 30 m av dd - 0.7 - - v v dd = 4.5 v, port 0 in external bus mode, ale, psen - i oh = - 3.2 ma v dd - 0.7 - - v i il low-level input current v i = 0.4 v, ports 1, 2, 3 - 1- - 50 m a i thl high-low transition current v i = 2 v, ports 1, 2, 3 [6] -- - 650 m a i li input leakage current 0.45 v < v i p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 43 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom [1] this parameter is measured only for initial quali?cation and after a design or process change that could affect this paramet er. [2] under steady state (non-transient) conditions, i ol must be externally limited as follows: a) maximum i ol per 8-bit port: 26 ma b) maximum i ol total for all outputs: 71 ma c) if i ol exceeds the test condition, v oh may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. [3] capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1 and 3. the noise due to external bus capacitance discharging into the port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. [4] load capacitance for port 0, ale and psen = 100 pf, load capacitance for all other outputs = 80 pf. [5] capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v dd - 0.7 speci?cation when the address bits are stabilizing. [6] pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curre nt reaches its maximum value when v i is approximately 2 v. [7] pin capacitance is characterized but not tested. ea = 25 pf (max). r pd pull-down resistance on pin rst 40 - 225 k w c iss input capacitance @ 1 mhz, t amb =25 c, v i =0v [7] - - 15 pf i dd(oper) operating supply current f osc = 12 mhz - - 3 ma f osc = 40 mhz - - 7 ma i dd(idle) idle mode supply current f osc = 12 mhz - - 1.7 ma f osc = 40 mhz - - 3 ma i dd(pd) power-down mode supply current minimum v dd =2v - - 15 m a table 44. static characteristics continued t amb = - 40 c to +85 c; v dd = 2.7 v to 5.5 v; v ss =0v symbol parameter conditions min typ max unit
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 44 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom (1) maximum i dd(oper) (2) typical i dd(oper) (3) maximum i dd(idle) (4) typical i dd(idle) fig 20. i dd vs. frequency clock frequency (mhz) (2) (1) (4) (3) 0 40 30 20 10 002aad196 4 2 6 8 i dd (ma) 0
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 45 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 9. dynamic characteristics [1] t cy(clk) = 1/f osc . table 45. dynamic characteristics over operating conditions: load capacitance for port 0, ale, and psen = 100 pf; load capacitance for all other outputs = 80 pf t amb = - 40 c to +85 c; v dd = 2.7 v to 5.5 v; v ss =0v [1] symbol parameter conditions min max unit f osc oscillator frequency 12-clock mode 0 40 mhz 6-clock mode 0 20 mhz t lhll ale pulse width 2t cy(clk) - 15 - ns t avll address valid to ale low time t cy(clk) - 15 - ns t llax address hold after ale low time t cy(clk) - 15 - ns t lliv ale low to valid instruction in time - 4t cy(clk) - 45 ns t llpl ale low to psen low time t cy(clk) - 15 - ns t plph psen pulse width 3t cy(clk) - 15 - ns t pliv psen low to valid instruction in time - 3t cy(clk) - 55 ns t pxix input instruction hold after psen time 0 - ns t pxiz input instruction ?oat after psen time - t cy(clk) - 20 ns t pxav psen to address valid time t cy(clk) - 8- ns t aviv address to valid instruction in time - 5t cy(clk) - 60 ns t plaz psen low to address ?oat time - 10 ns t rlrh rd low pulse width 6t cy(clk) - 30 - ns t wlwh wr low pulse width 6t cy(clk) - 30 - ns t rldv rd low to valid data in time - 5t cy(clk) - 50 ns t rhdx data hold after rd time 0 - ns t rhdz data ?oat after rd time - 2t cy(clk) - 12 ns t lldv ale low to valid data in time - 8t cy(clk) - 50 ns t avdv address to valid data in time - 9t cy(clk) - 75 ns t llwl ale low to rd or wr low time 3t cy(clk) - 15 3t cy(clk) + 15 ns t avwl address to rd or wr low time 4t cy(clk) - 30 - ns t whqx data hold after wr time t cy(clk) - 20 - ns t qvwh data output valid to wr high time 7t cy(clk) - 50 - ns t rlaz rd low to address ?oat time - 0 ns t whlh rd or wr high to ale high time t cy(clk) - 15 t cy(clk) + 15 ns
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 46 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 9.1 explanation of symbols each timing symbol has 5 characters. the ?rst character is always a t (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. a address c clock d input data h logic level high i instruction (program memory contents) l logic level low or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z high impedance (float) example: t avll = address valid to ale low time t llpl = ale low to psen low time fig 21. external program memory read cycle 002aaa548 port 2 psen ale a0 to a7 t llax t plaz t pxiz t llpl t aviv t avll t lliv t pliv t plph instr in a8 to a15 a8 to a15 a0 to a7 port 0 t pxix t pxav t lhll
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 47 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 22. external data memory read cycle ale psen port 0 port 2 rd a0 to a7 from ri to dpl data in a0 to a7 from pcl instr in p2[0] to p2[7] or a8 to a15 from dph a0 to a15 from pch t lldv 002aad704 t whlh t avdv t llwl t avll t avwl t rlrh t rldv t llax t rhdz t rhdx t rlaz fig 23. external data memory write cycle 002aad706 port 2 port 0 wr psen ale t lhll p2[0] to p2[7] or a8 to a15 from dph a0 to a7 from ri or dpl data out instr in t avll t avwl t llwl t llax t wlwh t qvwh t whqx t whlh a8 to a15 from pch a0 to a7 from pcl
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 48 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom table 46. external clock drive symbol parameter oscillator unit 40 mhz variable min max min max f osc oscillator frequency - - 0 40 mhz t cy(clk) clock cycle time 25 - - - ns t chcx clock high time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clcx clock low time 8.75 - 0.35t cy(clk) 0.65t cy(clk) ns t clch clock rise time - 10 - - ns t chcl clock fall time - 10 - - ns fig 24. external clock drive waveform (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907 table 47. serial port timing symbol parameter oscillator unit 40 mhz variable min max min max t xlxl serial port clock cycle time 0.3 - 12t cy(clk) - m s t qvxh output data set-up to clock rising edge time 117 - 10t cy(clk) - 133 - ns t xhqx output data hold after clock rising edge time 0- 2t cy(clk) - 15 - ns t xhdx input data hold after clock rising edge time 0- 0 - ns t xhdv input data valid to clock rising edge time - 117 - 10t cy(clk) - 133 ns
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 49 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 25. shift register mode timing waveforms 002aaa552 ale 0 instruction 1 2 3 4 5 6 7 8 01234567 valid valid valid valid valid valid valid valid t xlxl set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 26. test load example all other pins disconnected fig 27. i dd test condition, active mode 002aaa555 to dut to tester c l 002aaa556 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd v dd 8 dut
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 50 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom all other pins disconnected fig 28. i dd test condition, idle mode all other pins disconnected fig 29. i dd test condition, power-down mode 002aaa557 v dd v dd v dd p0 ea rst xtal2 (n.c.) clock signal xtal1 v ss i dd 8 dut 002aaa558 v dd v dd = 2 v v dd p0 ea rst xtal2 (n.c.) xtal1 v ss i dd v dd 8 dut
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 51 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 10. package outline fig 30. package outline sot129-1 (dip40) unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.1 0.6 0.62 0.60 0.69 0.63 0.089 0.19 0.02 0.16 051g08 mo-015 sc-511-40 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 52 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 31. package outline sot389-1 (lqfp44) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.45 0.30 0.20 0.12 10.1 9.9 0.8 12.15 11.85 1.14 0.85 7 0 o o 0.2 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot389-1 136e08 ms-026 00-01-19 02-06-07 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.14 0.85 d b p e e b 11 d h b p e h v m b d z d a z e e v m a 1 44 34 33 23 22 12 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 53 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom fig 32. package outline sot187-2 (plcc44) unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 54 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 11. abbreviations table 48. acronym list acronym description crc cyclic redundancy check eeprom electrically erasable programmable read-only memory emi electromagnetic interference iap in-application programming i/o input/output lsb least signi?cant bit msb most signi?cant bit pwm pulse width modulator rc resistance-capacitance reti return from interrupt sfr special function register uart universal asynchronous receiver/transmitter
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 55 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 12. revision history table 49. revision history document id release date data sheet status change notice supersedes p89v52x2_3 20090504 product data sheet - p89v52x2_2 modi?cations: ? t ab le 44 : replaced v th(hl) with v il ? t ab le 44 : v ih , removed xtal1, rst from conditions p89v52x2_2 20080522 product data sheet - p89v52x2_1 modi?cations: ? table 3: added registers fmcon, fmdata, fmadrh and fmadrl ? table 33: changed address of register fmcon to f4h ? figure 1: corrected xtal pin names ? figure 21: deleted super?uous arrows ? figure 22: added right arrow to t rlrh ? figure 23: deleted unwanted lines from data out p89v52x2_1 20080403 product data sheet - -
p89v52x2_3 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 03 4 may 2009 56 of 57 nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 13.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 13.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 13.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 14. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors p89v52x2 80c51 with 256 b ram, 192 b data eeprom ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 4 may 2009 document identifier: p89v52x2_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 8 6.1 special function registers . . . . . . . . . . . . . . . . . 8 6.2 memory organization . . . . . . . . . . . . . . . . . . . 11 6.3 system clock and clock options . . . . . . . . . . . 11 6.3.1 clock input options and recommended capacitor values for the oscillator . . . . . . . . . . 11 6.3.2 clock control register (ckcon) . . . . . . . . . . . 12 6.4 ale control . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.5 dual data pointers. . . . . . . . . . . . . . . . . . . . . . 13 6.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7.1 flash organization . . . . . . . . . . . . . . . . . . . . . 15 6.7.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 15 6.8.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.8.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.8.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.9 timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.9.1 capture mode . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.9.2 auto-reload mode (up or down-counter) . . . . . 21 6.9.3 programmable clock-out . . . . . . . . . . . . . . . . . 23 6.9.4 baud rate generator mode . . . . . . . . . . . . . . . 23 6.9.5 summary of baud rate equations . . . . . . . . . . 25 6.10 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.10.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.10.5 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.10.6 more about uart mode 1 . . . . . . . . . . . . . . . 27 6.10.7 more about uart modes 2 and 3 . . . . . . . . . 27 6.10.8 multiprocessor communications . . . . . . . . . . . 28 6.10.9 automatic address recognition . . . . . . . . . . . . 28 6.11 interrupt priority and polling sequence . . . . . . 30 6.12 power-saving modes . . . . . . . . . . . . . . . . . . . 32 6.12.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.12.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 33 6.13 data eeprom . . . . . . . . . . . . . . . . . . . . . . . . 33 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.13.2 register interface . . . . . . . . . . . . . . . . . . . . . . 34 6.13.3 mapping the data eeprom into code space. 34 6.13.4 reading the data eeprom . . . . . . . . . . . . . . 34 6.13.5 erasing a complete page (64 b). . . . . . . . . . . 35 6.13.6 data eeprom programming and erasing using the page register. . . . . . . . . . . . . . . . . . 35 6.13.7 data eeprom write enable. . . . . . . . . . . . . . 39 6.13.8 data eeprom security bits . . . . . . . . . . . . . . 39 6.13.9 summary of data eeprom commands. . . . . 39 6.14 user con?guration bytes. . . . . . . . . . . . . . . . . 40 6.15 ucfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.16 code security (csec) bits . . . . . . . . . . . . . . . 41 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 42 8 static characteristics . . . . . . . . . . . . . . . . . . . 42 9 dynamic characteristics . . . . . . . . . . . . . . . . . 45 9.1 explanation of symbols . . . . . . . . . . . . . . . . . 46 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 51 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 54 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 55 13 legal information . . . . . . . . . . . . . . . . . . . . . . 56 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 56 13.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14 contact information . . . . . . . . . . . . . . . . . . . . 56 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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